US 12,453,086 B2
Low resistivity metal contact stack
Annamalai Lakshmanan, Fremont, CA (US); Jacqueline S. Wrench, San Jose, CA (US); Feihu Wang, San Jose, CA (US); Yixiong Yang, Fremont, CA (US); Joung Joo Lee, San Jose, CA (US); and Srinivas Gandikota, Santa Clara, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Jun. 1, 2021, as Appl. No. 17/335,241.
Claims priority of provisional application 63/154,589, filed on Feb. 26, 2021.
Prior Publication US 2022/0277961 A1, Sep. 1, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. C23C 16/455 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H10B 12/00 (2023.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10B 12/488 (2023.02) [C23C 16/45553 (2013.01); H01L 21/02491 (2013.01); H01L 21/02631 (2013.01); H01L 21/2855 (2013.01); H01L 21/28556 (2013.01); H01L 21/28568 (2013.01); H10D 84/0149 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 15 Claims
OG exemplary drawing
 
1. A method of fabricating a microelectronic device, the method comprising depositing a metal contact stack by:
depositing a metal cap layer comprising tungsten on a substrate by a DC physical vapor deposition (PVD) process or an RF PVD process; and
depositing a molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer, wherein the substrate comprises a gate electrode on a gate dielectric layer on a surface of the substrate and a structure having at least one sidewall and a bottom, the at least one sidewall including a dielectric and the bottom including a metal, and the metal cap layer is deposited selectively on the bottom of the structure relative to the at least one sidewall.