US 12,453,085 B2
Semiconductor memory device having connection pattern between the bit line contact and the separation insulating pattern
Eunjung Kim, Suwon-si (KR); and Sohyun Park, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 5, 2023, as Appl. No. 18/093,568.
Claims priority of application No. 10-2022-0065304 (KR), filed on May 27, 2022.
Prior Publication US 2023/0389299 A1, Nov. 30, 2023
Int. Cl. H10B 12/00 (2023.01); H01L 23/528 (2006.01)
CPC H10B 12/485 (2023.02) [H01L 23/5283 (2013.01); H10B 12/482 (2023.02); H10B 12/488 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
active patterns spaced apart from each other in a first direction and a second direction intersecting the first direction, each of the active patterns including a central portion, a first end portion, and a second end portion;
bit line contacts spaced apart from each other in the first direction and the second direction, each of the bit line contacts being on a corresponding central portion;
separation insulating patterns between the bit line contacts, each of the separation insulating patterns being between adjacent ones of the bit line contacts in the first direction and the second direction;
intermediate insulating patterns between the bit line contacts and the separation insulating patterns, each of the intermediate insulating patterns being between one of the bit line contacts and one of the separation insulating patterns that are adjacent to each other in the first direction; and
connection patterns between the bit line contacts and the separation insulating patterns, each of the connection patterns being between one of the bit line contacts and one of the separation insulating patterns that are adjacent to each other in the second direction.