US 12,453,084 B2
Method for manufacturing a semiconductor memory
Chiang-Lin Shih, New Taipei (TW); Jhen-Yu Tsai, Kaohsiung (TW); and Tseng-Fu Lu, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Mar. 2, 2022, as Appl. No. 17/684,526.
Prior Publication US 2023/0284438 A1, Sep. 7, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/485 (2023.02) [H10B 12/0335 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory, comprising:
forming a data storage device having a surface;
forming a contact element over the surface of the data storage device and electrically connected to the data storage device, wherein the contact element has a first projecting area vertically projected by the contact element on the surface of the data storage device;
forming a data processing device over the surface of the data storage device and electrically connected to the contact element, wherein a size of the data storage device is greater than a size of the data processing device, wherein the data processing device has a second projecting area vertically projected by the data processing device on the surface of the data storage device, and the second projecting area is non-overlapped with the first projecting area;
disposing a plurality of connection layers on a surface of the data processing device, wherein a first connection layer of the connection layers is electrically connected the contact element with the data processing device; and
disposing a second connection layer, a third connection layer, and a fourth connection layer of the connection layers above the surface of the data storage device, wherein the data processing device comprise a top gate terminal electrically connected to the first connection layer, a drain terminal electrically connected to the second connection layer, a source terminal electrically connected to the third connection layer, and a bottom gate terminal electrically connected to the fourth connection layer.