US 12,453,083 B2
Semiconductor memory device and method of forming the same
Jonghyeok Kim, Suwon-si (KR); Jamin Koo, Suwon-si (KR); Beom Seo Kim, Suwon-si (KR); and Wonseok Yoo, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-Si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 4, 2023, as Appl. No. 18/149,800.
Claims priority of application No. 10-2022-0076243 (KR), filed on Jun. 22, 2022.
Prior Publication US 2023/0422487 A1, Dec. 28, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/482 (2023.02) [H10B 12/02 (2023.02); H10B 12/315 (2023.02); H10B 12/34 (2023.02); H10B 12/485 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
an active pattern defined by a device isolation pattern;
a bit line extending in a first direction on the device isolation pattern and the active pattern;
a bit line capping pattern including a first capping pattern, a second capping pattern, and a third capping pattern sequentially stacked on an upper surface of the bit line; and
a shield pattern covering one side of the bit line,
wherein an upper surface of the shield pattern is at a height lower than an upper surface of the first capping pattern.