US 12,453,082 B2
Semiconductor device having a cell separation pattern in contact with the bit line contact
Kiseok Lee, Suwon-si (KR); Jongmin Kim, Suwon-si (KR); Hyo-Sub Kim, Suwon-si (KR); Hui-Jung Kim, Suwon-si (KR); Sohyun Park, Suwon-si (KR); Junhyeok Ahn, Suwon-si (KR); Chan-Sic Yoon, Suwon-si (KR); Myeong-Dong Lee, Suwon-si (KR); Woojin Jeong, Suwon-si (KR); and Wooyoung Choi, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 14, 2023, as Appl. No. 18/109,442.
Claims priority of application No. 10-2022-0077227 (KR), filed on Jun. 24, 2022.
Prior Publication US 2023/0422486 A1, Dec. 28, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/482 (2023.02) [H10B 12/053 (2023.02); H10B 12/34 (2023.02); H10B 12/485 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a cell active pattern including a first portion and a second portion that are spaced apart from each other;
a gate structure between the first portion and the second portion of the cell active pattern;
a bit-line contact on the first portion of the cell active pattern;
a connection pattern on the second portion of the cell active pattern; and
a cell separation pattern in contact with the bit-line contact and the connection pattern,
wherein:
the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact,
an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and
a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.