US 12,453,081 B2
Method of forming a bit line structure
Jia Fang, Hefei (CN); Zhongming Liu, Hefei (CN); and Yexiao Yu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/915,991
Filed by ChangXin Memory Technologies, Inc., Hefei (CN)
PCT Filed Sep. 7, 2021, PCT No. PCT/CN2021/116908
§ 371(c)(1), (2) Date Sep. 29, 2022,
PCT Pub. No. WO2023/015639, PCT Pub. Date Feb. 16, 2023.
Claims priority of application No. 202110923884.8 (CN), filed on Aug. 12, 2021.
Prior Publication US 2024/0098982 A1, Mar. 21, 2024
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/482 (2023.02) [H10B 12/03 (2023.02); H10B 12/485 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure, comprising:
providing a substrate having a first region and a second region, forming a first insulating layer and a first isolation layer in sequence in the substrate, and forming a first trench in the first region;
filling the first trench;
removing the first isolation layer from the second region; and
forming a second trench at the first trench;
wherein
before removing the isolation layer from the second region, further comprising:
covering the first region with a second photoresist after etching bit line contact holes with a predetermined depth in a third region;
wherein
forming a second trench at the first trench comprises:
filling the bit line contact hole with a second polysilicon layer;
covering the second region with a third photoresist, and performing etchback to form the second trench at the first trench, wherein the second polysilicon layer located in the second region is not damaged.