US 12,453,078 B2
Semiconductor memory device
Teawon Kim, Suwon-si (KR); Yurim Kim, Suwon-si (KR); Seunghee Lee, Suwon-si (KR); Seungwoo Jang, Suwon-si (KR); and Yong-Suk Tak, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-Si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 27, 2023, as Appl. No. 18/175,198.
Claims priority of application No. 10-2022-0052115 (KR), filed on Apr. 27, 2022.
Prior Publication US 2023/0354605 A1, Nov. 2, 2023
Int. Cl. H10B 12/00 (2023.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/40 (2023.01)
CPC H10B 12/315 (2023.02) [H10B 12/34 (2023.02); H10B 41/27 (2023.02); H10B 43/27 (2023.02); H10B 41/10 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a bit line;
a channel pattern including a horizontal channel portion on the bit line; and a vertical channel portion vertically protruding from the horizontal channel portion;
a word line on the horizontal channel portion and on a sidewall of the vertical channel portion; and
a gate insulating pattern between the word line and the channel pattern,
wherein the channel pattern includes an oxide semiconductor and comprises first, second, and third channel layers stacked sequentially,
the first to third channel layers include a first metal,
the second channel layer further includes a second metal different from the first metal, and
at least a portion of the first channel layer contacts the bit line.