US 12,453,077 B2
Capacitor and memory device
Cheoljin Cho, Suwon-si (KR); Jaesoon Lim, Suwon-si (KR); Jaehyoung Choi, Hwaseong-si (KR); and Jungmin Park, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 28, 2024, as Appl. No. 18/675,175.
Application 18/675,175 is a continuation of application No. 18/205,715, filed on Jun. 5, 2023, granted, now 12,029,027.
Application 18/205,715 is a continuation of application No. 17/222,006, filed on Apr. 5, 2021, granted, now 11,678,476, issued on Jun. 13, 2023.
Claims priority of application No. 10-2020-0121326 (KR), filed on Sep. 21, 2020.
Prior Publication US 2024/0315003 A1, Sep. 19, 2024
Int. Cl. H10B 12/00 (2023.01); H10D 1/68 (2025.01)
CPC H10B 12/30 (2023.02) [H10D 1/682 (2025.01); H10D 1/694 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A capacitor, comprising:
a lower electrode;
a dielectric layer structure on the lower electrode; and
an upper electrode on the dielectric layer structure,
wherein the dielectric layer structure includes:
a first insert layer contacting the lower electrode, the first insert layer including at least one of Al, Ta, Nb, Mo, W, Ru, V, Y, Sc, or Gd,
a first stacked structure on the first insert layer and the first stacked structure includes a first layer, a second layer and a third layer sequentially stacked, and
a second insert layer on the first stacked structure and the second insert layer including at least one of Al, Ta, Nb, Mo, W, Ru, V, Y, Sc, or Gd, and
wherein the second layer includes hafnium or hafnium oxide.