US 12,453,076 B2
High-density 3D-DRAM cell with scaled capacitors
Mauricio Manfrini, Zhubei (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on May 24, 2022, as Appl. No. 17/751,937.
Application 17/751,937 is a continuation of application No. 17/086,628, filed on Nov. 2, 2020, granted, now 11,355,496.
Claims priority of provisional application 63/038,154, filed on Jun. 12, 2020.
Claims priority of provisional application 62/968,396, filed on Jan. 31, 2020.
Prior Publication US 2022/0285355 A1, Sep. 8, 2022
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/30 (2023.02) [H10B 12/488 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a first metal gate extending upward from the substrate;
a first bottom capacitor electrode disposed along a sidewall of the first metal gate over the substrate;
a lower capacitor dielectric structure disposed over the first bottom capacitor electrode; and
a first lower source/drain region disposed directly over the lower capacitor dielectric structure;
a first lower channel region disposed directly over the first lower source/drain region;
a first lower drain/source region disposed directly over the first lower channel region;
a second bottom capacitor electrode disposed along the sidewall of the first metal gate over the first lower drain/source region;
an upper capacitor dielectric structure disposed over the second bottom capacitor electrode;
a first upper source/drain region disposed directly over the second bottom capacitor electrode;
a first upper channel region disposed directly over the first upper source/drain region; and
a first upper drain/source region disposed directly over the first upper channel region.