US 12,453,073 B2
Semiconductor device
Hitoshi Kunitake, Kanagawa (JP); Takayuki Ikeda, Kanagawa (JP); and Takahiro Fukutome, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/616,441
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed May 25, 2020, PCT No. PCT/IB2020/054923
§ 371(c)(1), (2) Date Dec. 3, 2021,
PCT Pub. No. WO2020/245695, PCT Pub. Date Dec. 10, 2020.
Claims priority of application No. 2019-107085 (JP), filed on Jun. 7, 2019.
Prior Publication US 2022/0238525 A1, Jul. 28, 2022
Int. Cl. H01L 27/00 (2006.01); H10B 12/00 (2023.01); H10D 30/67 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01)
CPC H10B 12/00 (2023.02) [H10D 30/6734 (2025.01); H10D 30/6755 (2025.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first layer, a second layer, and a third layer over a substrate,
wherein a first transistor included in the first layer comprises a first semiconductor layer comprising Si,
wherein a second transistor included in the second layer comprises a second semiconductor layer comprising Ga,
wherein a third transistor included in the third layer comprises a third semiconductor layer comprising at least one of In and Zn,
wherein the first semiconductor layer of the first transistor is formed using the substrate,
wherein the second semiconductor layer of the second transistor is formed using a crystal obtained by crystal growth over the substrate, and
wherein the third semiconductor layer of the third transistor is over the first semiconductor layer and the second semiconductor layer.