| CPC H10B 12/00 (2023.02) [G06N 3/065 (2023.01); G11C 11/401 (2013.01); G11C 11/54 (2013.01); H10D 30/6755 (2025.01); H10D 84/83 (2025.01)] | 12 Claims |

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1. A semiconductor device comprising:
a first circuit comprising a first transistor, a second transistor, a third transistor, and a first capacitor,
wherein a first gate of the first transistor is electrically connected to a first input wiring,
wherein a second gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and a first terminal of the first capacitor,
wherein a first gate of the third transistor is electrically connected to a second input wiring,
wherein a second gate of the third transistor is electrically connected to the one of the source and the drain of the second transistor and the first terminal of the first capacitor,
wherein the first circuit is configured to hold a first potential of the first terminal of the first capacitor and the second gate of the first transistor when the second transistor is brought into an off state,
wherein the first circuit is configured to bring the first transistor into one of an on state and an off state in accordance with the first potential and a second potential input to the first input wiring,
wherein the first input wiring is electrically connected to a circuit configured to supply data to the first circuit, and
wherein the second input wiring is electrically connected to the circuit configured to supply data to the first circuit.
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