US 12,453,071 B2
Gate spacer structures for three-dimensional semiconductor devices
Fadoua Chafik, San Diego, CA (US); and Xiaochen Zhang, Carlsbad, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Apr. 26, 2022, as Appl. No. 17/660,758.
Prior Publication US 2023/0345692 A1, Oct. 26, 2023
Int. Cl. H10B 10/00 (2023.01); H10D 64/01 (2025.01)
CPC H10B 10/125 (2023.02) [H10D 64/015 (2025.01)] 31 Claims
OG exemplary drawing
 
1. An apparatus comprising a semiconductor device, wherein the semiconductor device comprises:
one or more static random-access memory (SRAM) transistors, each including a first gate spacer structure and a first gate;
one or more logic nominal transistors, each including a second gate spacer structure and a second gate; and
one or more logic gate-biased transistors, each including a third gate spacer structure, a third gate, a S/D epitaxy region adjacent to the third gate spacer structure, and a S/D contact adjacent to the third gate spacer structure and above the S/D epitaxy region, the S/D contact having a top surface and a bottom surface smaller than the top surface, wherein the first gate spacer structure has a different material composition than the second and the third gate spacer structures, the third gate spacer structure is thinner than the first gate spacer structure such that the bottom surface of the S/D contact is directly in contact with a top surface of the S/D epitaxy region, and wherein the one or more SRAM transistors, the one or more logic nominal transistors, and the one or more logic gate-biased transistors each have a same contacted poly pitch (CPP), wherein the third gate spacer structure comprises a plurality of spacer layers laterally adjacent to the third gate, the plurality of spacer layers extending vertically and arranged side-by-side with each other.