US 12,453,070 B2
FinFET SRAM cells with dielectric fins
Jhon Jhy Liaw, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 27, 2023, as Appl. No. 18/360,544.
Application 17/379,104 is a division of application No. 16/050,702, filed on Jul. 31, 2018, granted, now 11,069,692, issued on Jul. 20, 2021.
Application 18/360,544 is a continuation of application No. 17/379,104, filed on Jul. 19, 2021, granted, now 11,792,971.
Prior Publication US 2023/0371226 A1, Nov. 16, 2023
Int. Cl. H10D 84/85 (2025.01); H10B 10/00 (2023.01); H10D 30/62 (2025.01); H10D 89/10 (2025.01)
CPC H10B 10/12 (2023.02) [H10D 30/62 (2025.01); H10D 84/853 (2025.01); H10D 89/10 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
a memory cell oriented lengthwise along a first direction and widthwise along a second direction generally perpendicular to the first direction, wherein the memory cell includes:
a first dielectric fin, a second dielectric fin, a third dielectric fin, a fourth dielectric fin, and a fifth dielectric fin disposed in this order along the first direction and oriented lengthwise along the second direction, and wherein the first dielectric fin, the second dielectric fin, the third dielectric fin, the fourth dielectric fin, and the fifth dielectric fin are spaced a distance from one another in the first direction;
a first semiconductor fin structure disposed between the first dielectric fin and the second dielectric fin;
a second semiconductor fin structure disposed between the fourth dielectric fin and the fifth dielectric fin;
a third semiconductor fin structure disposed between the second dielectric fin and the third dielectric fin,
a fourth semiconductor fin structure disposed between the third dielectric fin and the fourth dielectric fin,
wherein the first semiconductor fin structure, the second semiconductor fin structure, the third semiconductor fin structure, and the fourth semiconductor fin structure are each oriented lengthwise along the second direction and spaced a distance from one another and from each of the first dielectric fin, the second dielectric fin, the third dielectric fin, the fourth dielectric fin, and the fifth dielectric fin in the first direction;
a first source/drain (S/D) contact disposed over and contacting an epitaxial feature over the first semiconductor fin structure, an epitaxial feature over the third semiconductor fin structure, and the second dielectric fin; and
a second S/D contact disposed over and contacting an epitaxial feature over the second semiconductor fin structure, an epitaxial feature over the fourth semiconductor fin structure, and the fourth dielectric fin.