US 12,452,999 B2
Circuit board
Seong Hwan Im, Seoul (KR); Seon Mo Gu, Seoul (KR); Ki Tae Kwon, Seoul (KR); and Chang Je Kim, Seoul (KR)
Assigned to LG INNOTEK CO., LTD., Seoul (KR)
Appl. No. 18/033,168
Filed by LG INNOTEK CO., LTD., Seoul (KR)
PCT Filed Oct. 22, 2021, PCT No. PCT/KR2021/014971
§ 371(c)(1), (2) Date Apr. 21, 2023,
PCT Pub. No. WO2022/086295, PCT Pub. Date Apr. 28, 2022.
Claims priority of application No. 10-2020-0137219 (KR), filed on Oct. 22, 2020; and application No. 10-2020-0137340 (KR), filed on Oct. 22, 2020.
Prior Publication US 2023/0403787 A1, Dec. 14, 2023
Int. Cl. H05K 1/02 (2006.01); H01Q 1/38 (2006.01)
CPC H05K 1/0271 (2013.01) [H01Q 1/38 (2013.01); H05K 2201/0191 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit board comprising:
a first substrate layer;
a second substrate layer disposed on the first substrate layer; and
a third substrate layer disposed under the first substrate layer;
wherein the second substrate layer includes:
a first inner circuit pattern layer disposed on the first substrate layer;
a first outermost circuit pattern layer disposed on the first inner circuit pattern layer; and
a first via disposed between the first inner circuit pattern layer and the first outermost circuit pattern layer,
wherein the third substrate layer includes:
a second inner circuit pattern layer disposed under the first substrate layer;
a second outermost circuit pattern layer disposed under the second inner circuit pattern layer; and
a second via disposed between the second inner circuit pattern layer and the second outermost circuit pattern layer,
wherein a thickness of each of the first and second outermost circuit pattern layers is greater than a thickness of each of the first and second inner circuit pattern layers, and
wherein a thickness of the first outermost circuit pattern layer is different from a thickness of the second outermost circuit pattern layer.