US 12,452,903 B2
Techniques for data multiplexing based on packet delay
Jelena Damnjanovic, Del Mar, CA (US); and Tao Luo, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 17, 2021, as Appl. No. 17/478,783.
Prior Publication US 2023/0087091 A1, Mar. 23, 2023
Int. Cl. H04W 72/20 (2023.01); H04W 72/1268 (2023.01); H04W 72/23 (2023.01); H04W 72/566 (2023.01)
CPC H04W 72/566 (2023.01) [H04W 72/1268 (2013.01); H04W 72/20 (2023.01); H04W 72/23 (2023.01)] 43 Claims
OG exemplary drawing
 
1. An apparatus for wireless communications at a first device, comprising:
one or more memories; and
one or more processors coupled with the one or more memories and configured to cause the first device to:
receive, from a second device, control signaling that indicates a set of parameter values associated with a prioritization procedure for a set of logical channels;
receive, from the second device, a grant that schedules a transmission of data; and
transmit the data to the second device in accordance with the grant, the data corresponding to the set of logical channels and multiplexed, for transmission, in accordance with a parameter value of the set of parameter values, the parameter value based at least in part on a packet delay associated with one or more logical channels of the set of logical channels, the packet delay determined based at least in part on a delay prediction.