| CPC H04W 72/25 (2023.01) [H04L 1/1812 (2013.01)] | 2 Claims |

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1. A user equipment, comprising:
a processor; and
a memory in electronic communication with the processor, wherein instructions stored in the memory are executable to:
monitor a physical sidelink control channel (PSCCH) for first sidelink control information (SCI) when a first timer is running, and
for the received first SCI,
in a case that HARQ feedback is enabled by the first SCI,
start a second timer upon an end of a physical sidelink feedback channel (PSFCH) transmission for the HARQ feedback,
start a third timer after an expiry of the second timer, and
monitor the PSCCH for second SCI when the third timer is running, and
in a case that the HARQ feedback is disabled by the first SCI,
start a fourth timer upon an end of a physical sidelink shared channel (PSSCH) transmission indicated in the first SCI,
start a fifth timer after an expiry of the fourth timer, and
monitor the PSCCH for the second SCI when the fifth timer is running.
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