| CPC H04W 4/80 (2018.02) [H04L 25/022 (2013.01); H04W 4/023 (2013.01)] | 20 Claims |

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1. A device, the device comprising processing circuitry coupled to storage, the processing circuitry configured to:
receive a packet from a reflector device, wherein the packet comprises an access code and a coded sequence of bits encoded using Gaussian Frequency Shift Keying (GFSK);
receive a tone signal from the reflector device;
calculate a first frequency offset estimation associated with the packet, based at least on the coded sequence of bits;
calculate a second frequency offset estimation associated with the tone signal;
calculate a difference between the first frequency offset estimation and the second frequency offset estimation; and
identify an allowable threshold range of the difference, and determine whether the difference is within the allowable threshold range to detect potential interference with the tone signal.
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