US 12,452,609 B2
Offset reduction for silicon microphones
Hong Chen, Pogöriach (AT); Benno Muehlbacher, Villach-St. Magdalen (AT); Michael Reinhold, Erlangen (DE); Juergen Roeber, Stegaurach (DE); and Andreas Wiesbauer, Pörtschach a. W. (AT)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Jan. 9, 2023, as Appl. No. 18/151,628.
Prior Publication US 2024/0236585 A1, Jul. 11, 2024
Int. Cl. H04R 19/00 (2006.01); H04R 3/04 (2006.01)
CPC H04R 19/005 (2013.01) [H04R 3/04 (2013.01); H04R 2201/003 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A microphone comprising:
a first resistor circuit for receiving a bias voltage;
an offset reduction circuit coupled to the first resistor circuit;
a second resistor circuit coupled to the offset reduction circuit;
an amplifier coupled to the second resistor circuit configured for receiving an input signal and generating an output signal; and
a capacitor circuit coupled to the amplifier, the offset reduction circuit, and the second resistor circuit.
 
13. A microphone comprising:
a switched capacitor resistor circuit for receiving a bias voltage;
a diode-based resistor circuit coupled to the switched capacitor resistor circuit;
an amplifier coupled to the diode-based resistor circuit configured for receiving an input signal and generating an output signal; and
a capacitor circuit coupled to the amplifier and the diode-based resistor circuit in a feedback loop configuration.