US 12,452,563 B2
Solid-state imaging device, method for driving solid-state imaging device, and electronic apparatus
Ryotaro Hotta, Kusatsu (JP); Shunsuke Okura, Kusatsu (JP); Ken Miyauchi, Tokyo (JP); Hideki Owada, Tokyo (JP); Sangman Han, Tokyo (JP); and Isao Takayanagi, Tokyo (JP)
Assigned to BRILLNICS SINGAPORE PTE. LTD., Singapore (SG); and THE RITSUMEIKAN TRUST, Kyoto (JP)
Filed by Brillnics Singapore Pte. Ltd., Singapore (SG); and THE RITSUMEIKAN TRUST, Kyoto (JP)
Filed on Apr. 25, 2024, as Appl. No. 18/646,263.
Claims priority of application No. 2023-071507 (JP), filed on Apr. 25, 2023.
Prior Publication US 2024/0365027 A1, Oct. 31, 2024
Int. Cl. H04N 25/78 (2023.01); H04N 25/59 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01)
CPC H04N 25/78 (2023.01) [H04N 25/59 (2023.01); H04N 25/772 (2023.01); H04N 25/778 (2023.01)] 16 Claims
OG exemplary drawing
 
1. A solid-state imaging device comprising:
a readable pixel adapted to produce a plurality of read-out signals as a pixel signal, each of the plurality of read-out signals being formed of a signal at a reference level and a signal at a signal level;
a pixel signal processing part for processing the pixel signal read out from the readable pixel,
wherein the pixel signal processing part includes:
an input node for receiving the pixel signal read out from the readable pixel input thereto;
a connection node connected to a next-stage circuit;
an operational amplifier having an inverting input terminal and a non-inverting input terminal;
a first node connected to the non-inverting input terminal of the operational amplifier;
a second node;
a third node connected to an output terminal of the operational amplifier and the connection node;
a first auto-zero switch connected between the third node and the first node;
an auto-zero capacitor connected between the first node and the second node;
a second auto-zero switch connected between the second node and a predetermined bias potential, the second auto-zero switch being turned on and off in phase with the first auto-zero switch;
a feedback capacitor connected between the third node and the second node; and
a sampling capacitor connected between the second node and the input node,
wherein the first auto-zero switch and the second auto-zero switch are kept in ON state during an auto-zero period including a reset function.