US 12,452,555 B2
Solid-state imaging element
Ryo Tamaki, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 18/577,821
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Jan. 31, 2022, PCT No. PCT/JP2022/003521
§ 371(c)(1), (2) Date Jan. 9, 2024,
PCT Pub. No. WO2023/007772, PCT Pub. Date Feb. 2, 2023.
Claims priority of application No. 2021-121209 (JP), filed on Jul. 26, 2021.
Prior Publication US 2024/0323554 A1, Sep. 26, 2024
Int. Cl. H04N 25/616 (2023.01); H04N 25/709 (2023.01); H04N 25/78 (2023.01)
CPC H04N 25/616 (2023.01) [H04N 25/709 (2023.01); H04N 25/78 (2023.01)] 17 Claims
OG exemplary drawing
 
1. A solid-state imaging element, comprising:
a first capacitance element and a second capacitance element;
a previous-stage circuit configured to generate a specific reset level and a signal level in accordance with an amount of exposure in order and cause the first capacitance element and the second capacitance element to hold the specific reset level and the signal level;
a next-stage reset transistor configured to initialize a level of a next-stage node connected to one of the first capacitance element or the second capacitance element to a specific potential that is lower than a power source voltage of the previous-stage circuit;
a next-stage circuit configured to read the specific reset level and the signal level via the next-stage node and output the specific reset level and the signal level to a vertical signal line;
a reference voltage generation circuit configured to generate a reference voltage with reference to the specific potential; and
a comparator configured to compare the reference voltage and a potential of the vertical signal line.