US 12,452,223 B2
Systems and methods for communicating encrypted time-related data
Choon Yip Soo, Bayan Lepas (MY); Su Wei Lim, Bayan Lepas (MY); Si Xing Saw, Bukit Mertajam (MY); and Markos Papadonikolakis, London (GB)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2021, as Appl. No. 17/559,875.
Prior Publication US 2022/0116373 A1, Apr. 14, 2022
Int. Cl. H04L 9/40 (2022.01)
CPC H04L 63/068 (2013.01) [H04L 63/0428 (2013.01); H04L 63/108 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
a counter, wherein the counter provides an elapsed time to scheduler circuitry;
encryption circuitry to encrypt a data packet, wherein the encryption circuitry indicates an initial elapsed time upon receipt of the data packet; and
the scheduler circuitry to receive the encrypted data packet from the encryption circuitry, wherein the scheduler circuitry:
monitors a duration of time associated with egress of the encrypted data packet, wherein the scheduler circuitry determines the duration of time associated with egress of the encrypted data packet based on a difference between the initial elapsed time indicated by the encryption circuitry and the elapsed time provided by the counter;
holds the encrypted data packet until the duration of time matches a threshold duration of time; and
transmits the encrypted data packet in response to the duration of time matching the threshold duration of time.