US 12,452,186 B2
Method and apparatus to assign and check anti-replay sequence numbers using load balancing
Niall McDonnell, Limerick (IE); Pravin Pathak, Bridgewater, NJ (US); Rahul Shah, Chandler, AZ (US); and Declan Doherty, Clondalkin (IE)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 16, 2021, as Appl. No. 17/553,543.
Prior Publication US 2023/0198912 A1, Jun. 22, 2023
Int. Cl. H04L 47/70 (2022.01); H04L 9/40 (2022.01); H04L 47/2441 (2022.01); H04L 47/27 (2022.01); H04L 47/34 (2022.01)
CPC H04L 47/34 (2013.01) [H04L 47/2441 (2013.01); H04L 47/27 (2013.01); H04L 63/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
circuitry to assign sequence numbers to packets of traffic flows, wherein a first sequence number is assigned to a first packet based on a determination that the first packet is within a first traffic flow mapped to a first secure channel, and wherein the first sequence number is within a set of sequence numbers allocated to the first secure channel and maintained by the circuitry, the circuitry to distribute the packets of traffic flows to be processed among a plurality of processor cores, wherein the first sequence number assigned to the first packet is to be inserted in header of the first packet by a processor core within the plurality of processor cores; and
the plurality of processor cores to process the packets of traffic flows.