US 12,452,110 B2
Fast common mode charging
Charles L. Wang, Los Altos, CA (US); Yi-Hsiu E. Chen, San Jose, CA (US); Yu-Yau Guo, San Jose, CA (US); and Wei-Ming Lee, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jun. 21, 2023, as Appl. No. 18/339,232.
Prior Publication US 2024/0430138 A1, Dec. 26, 2024
Int. Cl. H04L 25/02 (2006.01); G06F 13/40 (2006.01)
CPC H04L 25/0276 (2013.01) [G06F 13/4072 (2013.01); H04L 25/0278 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a transmitter circuit configured to transmit a differential signal on a communication bus that includes a true signal line and a complement signal line;
a measurement circuit configured to measure respective voltage levels of the true signal line and the complement signal line; and
a control circuit configured to, in response to exiting a sleep mode, select one of a plurality of operation modes using the respective voltage levels of the true signal line and the complement signal line, wherein the operation modes specify characteristics of one or more pulses for charging the true signal line and complement signal line prior to transmitting the differential signal; and
wherein the transmitter circuit is further configured to adjust the respective voltage levels of the true signal line and the complement signal line based on a selected operation mode of the plurality of operation modes.