US 12,451,912 B2
Generalized digital compensator for wireless systems
Kevin Chuang, Belmont, MA (US); Marwen Ben Rejeb, Nepean, CA (US); Ahmed M. R. A. Raslan, Ottawa (CA); Xiao Yu Wang, Watertown, MA (US); and Kaustubh Pradeepkumar Mundhada, Kaggadasapura (IN)
Assigned to Analog Devices International Unlimited Company, Limerick (IE)
Filed by Analog Devices International Unlimited Company, Limerick (IE)
Filed on Jul. 28, 2023, as Appl. No. 18/361,697.
Claims priority of provisional application 63/489,690, filed on Mar. 10, 2023.
Prior Publication US 2024/0305322 A1, Sep. 12, 2024
Int. Cl. H04B 1/04 (2006.01); H04B 1/00 (2006.01); H04L 27/26 (2006.01)
CPC H04B 1/0475 (2013.01) [H04B 1/0075 (2013.01); H04L 27/2614 (2013.01); H04B 2001/0408 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A digital predistortion system configured to distort a power amplifier input signal prior to being input to a power amplifier, the digital predistortion system comprising:
a compensator comprising a plurality of processing circuit blocks, wherein each processing circuit block of the plurality of processing circuit blocks is configured to implement a transformation function to modify a characteristic of an input signal that is input to the compensator, wherein the transformation function is implemented as a set of neurons, and wherein each neuron of the set of neurons comprises:
a first processor configured to execute a first operation that transforms a complex input signal to a first complex intermediate signal;
a second processor configured to execute a second operation that transforms the first complex intermediate signal to a real intermediate signal;
a third processor configured to execute a third operation that transforms the real intermediate signal to a second complex intermediate signal;
a multiplier that combines the first complex intermediate signal and the second complex intermediate signal to obtain an output signal; and
a fourth processor between the second processor and the third processor, the fourth processor configured to execute a fourth operation that transforms the real intermediate signal to a modified real intermediate signal, and wherein the third operation transforms the real intermediate signal by transforming the modified real intermediate signal to the second complex intermediate signal,
wherein each processing circuit block comprises an adder configured to combine the output signal of each neuron from the set of neurons to generate an output of the transformation function.