US 12,451,903 B2
ADC error compensation using powers of ADC output
Robert van Veldhoven, Valkenswaard (NL); and Maarten Jelmar Molendijk, Eindhoven (NL)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Jun. 27, 2023, as Appl. No. 18/215,003.
Prior Publication US 2025/0007532 A1, Jan. 2, 2025
Int. Cl. H03M 1/00 (2006.01); H03M 3/00 (2006.01)
CPC H03M 3/322 (2013.01) [H03M 3/458 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
an analog-to-digital converter (ADC) including:
an input terminal configured to receive an analog input signal, and
an output terminal configured to output a digital signal x, wherein the digital signal x includes a digital approximation of the analog input signal; and
an error correction system connected to the ADC, the error correction system including a first input terminal configured to receive an Nth powered version of the digital signal x, wherein N is a whole number equal to or greater than two, wherein the error correction system is configured to:
use the Nth powered version of the digital signal x to determine a correction value; and
modify the digital signal x to generate a corrected digital signal by applying the correction value to compensate for analog-to-digital conversion errors occurring within the ADC;
wherein the error correction system includes a neural network configured to determine the correction value.