US 12,451,897 B1
CAP-RAM ADC sharing
Krishnamurthy Subramanian, Saratoga, CA (US)
Assigned to PIMIC, Cupertino, CA (US)
Filed by Krishnamurthy Subramanian, Saratoga, CA (US)
Filed on Oct. 30, 2023, as Appl. No. 18/385,236.
Claims priority of provisional application 63/438,040, filed on Jan. 10, 2023.
Claims priority of provisional application 63/420,794, filed on Oct. 31, 2022.
Int. Cl. H03M 1/12 (2006.01); G11C 7/16 (2006.01)
CPC H03M 1/1245 (2013.01) [G11C 7/16 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A charge-domain, in-memory computing circuit, comprising:
an analog-to-digital converter connected by a first switch to a first CAP-RAM macro, and connected by a second switch to a second CAP-RAM macro;
wherein the switches are controlled to alternately connect the ADC to either the first CR or to the second CR to sample capacitive charge maintained by (each slice) one and then the other of the two CAP-RAMs; and
wherein, during a first period of time that the ADC is sampling capacitive charge maintained by the first CAP-RAM, the second CAP-RAM performs an in-memory computing (IMC) operation.