US 12,451,895 B2
Mismatch shaping apparatus and method for binary coded digital-to-analog converters
Jyotindra R. Shakya, Corvallis, OR (US); and Gabor C. Temes, Corvallis, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Oregon State University, Corvallis, OR (US)
Filed on Oct. 26, 2023, as Appl. No. 18/495,711.
Claims priority of provisional application 63/381,534, filed on Oct. 28, 2022.
Prior Publication US 2024/0146320 A1, May 2, 2024
Int. Cl. H03M 1/06 (2006.01); H03M 1/66 (2006.01); H03M 3/00 (2006.01)
CPC H03M 1/0604 (2013.01) [H03M 1/066 (2013.01); H03M 1/0668 (2013.01); H03M 3/464 (2013.01); H03M 1/66 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a mismatch shaping circuitry to receive an N-bit binary input bits and to generate an (N+1)-bit digital output; and
a digital-to-analog converter to receive the (N+1)-bit digital output and to generate an analog output, wherein the mismatch shaping circuitry is to encode the (N+1)-bit digital output to shape mismatch errors in the digital-to-analog converter.