US 12,451,889 B2
Multi-mode frequency division circuit
Qiuyan Zu, Shanghai (CN); Gang Yan, Shanghai (CN); Yong Wang, Shanghai (CN); and Pengzhan Zhang, Shanghai (CN)
Assigned to Montage Electronics (Shanghai) Co., Ltd., Shanghai (CN)
Filed by Montage Electronics (Shanghai) Co., Ltd., Shanghai (CN)
Filed on Aug. 1, 2024, as Appl. No. 18/792,540.
Claims priority of application No. 202310982080.4 (CN), filed on Aug. 4, 2023.
Prior Publication US 2025/0047287 A1, Feb. 6, 2025
Int. Cl. H03K 21/02 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01)
CPC H03K 21/02 (2013.01) [H03K 3/037 (2013.01); H03K 19/20 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A multi-mode frequency division circuit, comprising:
a frequency division factor processor, receiving a frequency division factor, decomposing the frequency division factor to obtain a first sub-frequency division factor and a second sub-frequency division factor, and selectively outputting the first sub-frequency division factor or the second sub-frequency division factor according to a frequency division clock signal;
a frequency divider, coupled to the frequency division factor processor, receiving a clock signal, performing frequency division on the clock signal based on the first sub-frequency division factor or the second sub-frequency division factor to generate the frequency division clock signal; and
a logic operator, sequentially sampling the frequency division clock signal according to a rising edge and a falling edge of the clock signal to generate a first signal and a second signal, and generating an output clock signal according to the first signal, the second signal, and an indication signal.