US 12,451,888 B1
Ripple carry adder with ferroelectric or paraelectric wide-input minority or majority gates
Amrita Mathuriya, Portland, OR (US); Ikenna Odinaka, Durham, NC (US); Rajeev Kumar Dokania, Beaverton, OR (US); Rafael Rios, Austin, TX (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Sep. 3, 2021, as Appl. No. 17/467,026.
Application 17/467,026 is a continuation of application No. 17/465,781, filed on Sep. 2, 2021.
Int. Cl. H03K 19/23 (2006.01); G06F 7/501 (2006.01); H10D 1/68 (2025.01)
CPC H03K 19/23 (2013.01) [G06F 7/501 (2013.01); H10D 1/682 (2025.01); H10D 1/694 (2025.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first 1-bit adder to receive a first input, a second input, and a third input, wherein the first input is a first operand, wherein the second input is a second operand, wherein the third input is a carry-in input, wherein the third input is coupled to ground, and wherein the first 1-bit adder is to generate a first sum output and a first carry output; and
a second 1-bit adder coupled to the first 1-bit adder, wherein the second 1-bit adder is to receive a fourth input, a fifth input, and a sixth input, wherein the fourth input is a third operand, wherein the fifth input is a fourth operand, wherein the sixth input is a carry-in input, wherein the sixth input is coupled to the first sum output, wherein the second 1-bit adder is to generate a second sum output and a second carry output, wherein the first 1-bit adder includes a first set of input capacitors with non-linear polar material, wherein the second 1-bit adder includes a second set of input capacitors with the non-linear polar material, wherein the first set of input capacitors include at least three input capacitors, wherein first terminals of the at least three input capacitors are directly connected without magnets to the first input, the second input, and the third input respectively, and wherein second terminals of the at least three input capacitors are directly connected without magnets to a node.