US 12,451,886 B2
Buffer circuit capable of reducing noise
Jin Ha Hwang, Icheon-si (KR); Soon Sung An, Icheon-si (KR); Junseo Jang, Icheon-si (KR); and Jaehyeong Hong, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 21, 2023, as Appl. No. 18/516,615.
Application 18/516,615 is a division of application No. 17/514,789, filed on Oct. 29, 2021, granted, now 11,843,373.
Claims priority of application No. 10-2021-0082019 (KR), filed on Jun. 24, 2021.
Prior Publication US 2024/0097685 A1, Mar. 21, 2024
Int. Cl. H03K 19/0185 (2006.01); H03K 19/003 (2006.01)
CPC H03K 19/018521 (2013.01) [H03K 19/00361 (2013.01)] 5 Claims
OG exemplary drawing
 
1. An enable signal generation circuit comprising:
a buffer circuit configured to invert an input signal to generate an output signal with a voltage level that varies between a first voltage and a second voltage different from the first voltage, configured to adjust voltage levels of the first voltage and the second voltage based on the input signal and the output signal in a first operation mode, and configured to maintain the voltage levels of the first voltage and the second voltage in a second operation mode;
a delay circuit configured to delay the output signal and generate a delayed output signal; and
a trigger circuit configured to generate an enable signal based on the output signal and the delayed output signal.