| CPC H03K 19/00346 (2013.01) [H03K 3/037 (2013.01); H03K 19/20 (2013.01); H04L 25/03 (2013.01)] | 20 Claims |

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1. A data transmission circuit, comprising:
a data processing circuit, configured to receive a first data signal in a parallel state and convert the first data signal into a second data signal in a serial state; and
a data driving circuit comprising a driving main circuit and a driving regulation circuit, wherein the driving regulation circuit is configured to reduce, in response to the driving regulation circuit being in an enabled state, a voltage difference of the second data signal, to shorten a charging and discharging time and implement driving enhancement, and the driving main circuit is configured to perform driving on an enhanced second data signal to obtain a target transmission signal.
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