US 12,451,881 B2
Receiver circuit, corresponding isolated driver device, electronic system and method of decoding a differential signal into a digital output signal
Carlo Curina, Bareggio (IT); Valerio Bendotti, Vilminore di Scalve (IT); Nicola De Campo, Cura Carpignano (IT); and Valerio Gennari Santori, Milan (IT)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Dec. 1, 2023, as Appl. No. 18/526,776.
Claims priority of application No. 102022000025200 (IT), filed on Dec. 7, 2022.
Prior Publication US 2024/0195405 A1, Jun. 13, 2024
Int. Cl. H03K 17/22 (2006.01); H03K 5/24 (2006.01); H03K 19/0185 (2006.01)
CPC H03K 17/223 (2013.01) [H03K 5/2454 (2013.01); H03K 5/2481 (2013.01); H03K 19/018514 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising a receiver circuit, the receiver circuit including:
a pair of input nodes configured to receive a differential signal therebetween, the differential signal including spikes of a first polarity and spikes of a second polarity;
an output node configured to produce a digital output signal as a function of the differential signal;
a first comparator circuit configured to receive the differential signal and to produce an intermediate set signal that includes a pulse at each spike of the differential signal having the first polarity;
a second comparator circuit configured to receive the differential signal and to produce an intermediate reset signal that includes a pulse at each spike of the differential signal having the second polarity;
a logic circuit configured to receive the intermediate set signal, the intermediate reset signal and the digital output signal, and to generate a corrected set signal and a corrected reset signal; and
an output control circuit configured to receive the corrected set signal and the corrected reset signal, and further configured to assert the digital output signal based on the corrected set signal and the corrected reset signal.