US 12,451,875 B2
High-voltage Schmitt trigger
Sanmitra Bharat Naik, Bangalore (IN); and Asif Iqbal, Bangalore (IN)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Jan. 23, 2024, as Appl. No. 18/419,686.
Prior Publication US 2025/0240000 A1, Jul. 24, 2025
Int. Cl. H03K 3/3565 (2006.01); H03K 3/356 (2006.01); H10D 30/63 (2025.01); H10D 30/65 (2025.01); H10D 86/00 (2025.01)
CPC H03K 3/3565 (2013.01) [H03K 3/356104 (2013.01); H10D 30/637 (2025.01); H10D 30/65 (2025.01); H10D 86/201 (2025.01); H03K 2217/0018 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A structure comprising:
a first p-channel field effect transistor (PFET) and a second PFET connected in series to a positive voltage rail;
a first n-channel field effect transistor (NFET) and a second NFET connected in series between a ground rail and the second PFET,
wherein gates of the first PFET and the first NFET are connected to an input node to receive an input voltage, and
wherein gates of the second PFET and the second NFET are connected to receive different reference voltages;
an output node connected to a first intermediate node between the second PFET and the second NFET;
a third PFET connected between the ground rail and a second intermediate node between the first PFET and the second PFET;
a fourth PFET connected between a gate of the third PFET and the output node;
a third NFET connected between the positive voltage rail and a third intermediate node between the first NFET and the second NFET; and
a fourth NFET connected between a gate of the third NFET and the output node.