US 12,451,873 B2
Quadrature duty cycle correction circuit
Andrew Weil, San Diego, CA (US); Jaswinder Singh, San Diego, CA (US); Sameer Wadhwa, San Diego, CA (US); and Dongwon Seo, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on May 4, 2023, as Appl. No. 18/312,317.
Prior Publication US 2024/0372535 A1, Nov. 7, 2024
Int. Cl. H03K 3/017 (2006.01); H03K 5/156 (2006.01)
CPC H03K 3/017 (2013.01) [H03K 5/1565 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A duty cycle correction circuit comprising:
an internal node;
an inverter configured to invert a voltage of the internal node to produce an output clock signal having a corrected duty cycle;
a first transistor coupled in series with a second transistor between the internal node and ground, wherein a first node for a first quadrature clock signal is coupled to a gate of the first transistor and a second node for a second quadrature clock signal is coupled to a gate of the second transistor, wherein the first quadrature clock signal is a 0° quadrature clock signal and the second quadrature clock signal is a complement of a 90° quadrature clock signal that is delayed by one-quarter of a period of the output clock signal with respect to the 0° quadrature clock signal; and
a third transistor coupled in series with a fourth transistor between the internal node and ground, wherein a third node for a third quadrature clock signal is coupled to a gate of the third transistor and a fourth node for a fourth quadrature clock signal is coupled to a gate of the fourth transistor.