US 12,451,872 B2
Multi-phase clock generation circuit
Sheng Chen, Shenzhen (CN); and Theng Tee Yeo, Singapore (SG)
Assigned to HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed by Huawei Technologies Co., Ltd., Shenzhen (CN)
Filed on Jun. 21, 2023, as Appl. No. 18/338,893.
Application 18/338,893 is a continuation of application No. PCT/CN2020/139332, filed on Dec. 25, 2020.
Prior Publication US 2023/0336163 A1, Oct. 19, 2023
Int. Cl. H03K 3/012 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01)
CPC H03K 3/012 (2013.01) [H03K 3/037 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multi-phase clock generation circuit comprising:
a first loop;
a plurality of first logic gates coupled in series in the first loop, wherein the first logic gates are NOR gates or NAND gates, and wherein each of the first logic gates comprises:
a first selection signal input end electrically coupled to a first output end of a first logic gate of a first previous stage;
a first clock signal input end configured to receive input clock signals; and
a second output end, configured to output multi-phase clock signals; and
a plurality of first latches disposed in the first loop and configured to latch a first signal received at a first selection signal input end of at least one first logic gate of the first logic gates.