US 12,451,871 B2
Semiconductor device
Kwanyeob Chae, Suwon-si (KR); Chulwoo Kim, Seoul (KR); Yoonjae Choi, Seoul (KR); and Kyeongkeun Kang, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR); and Korea University Research and Business Foundation, Seoul (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 22, 2022, as Appl. No. 18/087,439.
Claims priority of application No. 10-2022-0048717 (KR), filed on Apr. 20, 2022.
Prior Publication US 2023/0344417 A1, Oct. 26, 2023
Int. Cl. H03K 3/012 (2006.01); H03K 17/687 (2006.01)
CPC H03K 3/012 (2013.01) [H03K 17/6872 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
an equalizer circuit configured to output a first control signal corresponding to a first bit of original two-bit data and a second control signal corresponding to a second bit of the original two-bit data; and
a driver circuit comprising a plurality of pull-up transistors connected between an output node and a first power node configured to provide a first power supply voltage, and a plurality of pull-down transistors connected between the output node and a second power node configured to provide a second power supply voltage, wherein the second power supply voltage is lower than the first power supply voltage, and the driver circuit is connected to the equalizer circuit in series,
wherein the plurality of pull-up transistors and the plurality of pull-down transistors are configured to respectively turn on and off according to the first control signal or the second control signal,
wherein the plurality of pull-up transistors comprises a first pull-up transistor and a second pull-up transistor connected to each other in parallel, between the first power node and the output node, and a third pull-up transistor and a fourth pull-up transistor connected to each other in series, between the first power node and the output node, and the first pull-up transistor and the third pull-up transistor are configured to turn on and off according to the first control signal which is provided to the first pull-up transistor and the third pull-up transistor, and
wherein the plurality of pull-down transistors comprises a first pull-down transistor and a second pull-down transistor connected to each other in parallel, between the second power node and the output node.