US 12,451,861 B2
Wafer level package
Robert Felix Bywalez, Munich (DE); Karl Nicolaus, Zorneding (DE); Ilya Lukashov, Munich (DE); and Luis Maier, Munich (DE)
Assigned to RF360 Singapore Pte. Ltd., Republic Plaza (SG)
Appl. No. 17/770,982
Filed by RF360 SINGAPORE PTE. LTD., Republic Plaza (SG)
PCT Filed Oct. 30, 2020, PCT No. PCT/EP2020/080555
§ 371(c)(1), (2) Date Apr. 21, 2022,
PCT Pub. No. WO2021/089434, PCT Pub. Date May 14, 2021.
Claims priority of application No. 10 2019 129 791.5 (DE), filed on Nov. 5, 2019.
Prior Publication US 2025/0150054 A1, May 8, 2025
Int. Cl. H03H 9/02 (2006.01)
CPC H03H 9/02574 (2013.01) [H03H 9/02992 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A wafer level package, comprising:
a substrate (SU) having a functional layer and electric device structures (DS) realized in the functional layer, on the functional layer or under the functional layer;
a first package layer (PL1) applied on the substrate, the first package layer defining cavities (CV) between the substrate and the first package layer, at least part of the device structures being arranged in the cavities;
a second package layer (PL2) applied over a surface of the first package layer;
pads (PD) arranged on the substrate and connected to the device structures, a partial area of each pad forming a respective contact area that is not covered by the first package layer or the second package layer;
an interconnect structure (IS) deposited on each respective contact area and extending up to an interconnect height (hi) over the substrate, the interconnect height being higher than a package height (hp) of the first package layer and the second package layer over the substrate; and
solder caps (SC) disposed at a respective distal end of each respective interconnect structure.