US 12,451,857 B2
Attenuation circuit
Xin Yang, Houten (NL); Dominicus Martinus Wilhelmus Leenaerts, Riethoven (NL); and Rana Azhar Shaheen, Caen (FR)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Nov. 1, 2022, as Appl. No. 18/051,596.
Claims priority of application No. 21306663 (EP), filed on Nov. 30, 2021.
Prior Publication US 2023/0170871 A1, Jun. 1, 2023
Int. Cl. H03H 7/25 (2006.01); H03F 3/19 (2006.01)
CPC H03H 7/255 (2013.01) [H03F 3/19 (2013.01); H03F 2200/451 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An attenuation circuit comprising:
a connection-node for connecting to an RF connection;
a first-control-node configured to receive a first-control-signal;
a second-control-node configured to receive a second-control-signal;
an internal-node;
a reference-node for connecting to a reference terminal;
an isolation-capacitor connected in series between the connection-node and the internal-node;
a first-bias-resistor connected in series between the first-control-node and the internal-node;
a second-bias-resistor connected in series between the internal-node and the second-control-node;
a first-attenuation-diode connected in series between the first-control-node and the internal-node, wherein the anode of the first-attenuation-diode is closest to the first-control-node, and wherein the first-attenuation-diode is connected in parallel with the first-bias-resistor;
a second-attenuation-diode connected in series between the internal-node and the second-control-node, wherein the anode of the second-attenuation-diode is closest to the internal-node, and wherein the second-attenuation-diode is connected in parallel with the second-bias-resistor;
a first-decoupling-capacitor connected in series between the first-control-node and the reference-node; and
a second-decoupling-capacitor connected in series between the second-control-node and the reference-node.