US 12,451,814 B2
NSN detection in primary-side-controlled AC-DC converter
Arun Khamesra, Bangalore (IN); Hariom Rai, Bangalore (IN); and Pulkit Shah, Bangalore (IN)
Assigned to Cypress Semiconductor Corporation, San Jose, CA (US)
Filed by Cypress Semiconductor Corporation, San Jose, CA (US)
Filed on Jul. 17, 2023, as Appl. No. 18/353,753.
Claims priority of application No. 202311011905 (IN), filed on Feb. 22, 2023.
Prior Publication US 2024/0283370 A1, Aug. 22, 2024
Int. Cl. H02M 3/335 (2006.01); H02M 1/08 (2006.01); H02M 7/217 (2006.01)
CPC H02M 3/33592 (2013.01) [H02M 1/08 (2013.01); H02M 3/33523 (2013.01); H02M 7/217 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating an AC-DC converter, the method comprising:
sensing on a drain node of a synchronous rectifier (SR) on a secondary-side of the AC-DC converter a SR_DRAIN voltage greater than a bus voltage (VBUS_IN) output from the AC-DC converter;
generating a first integration (volt-sec) signal based on a time and voltage for which the SR_DRAIN voltage is greater than VBUS_IN;
generating a second integration (integ_resetb) signal having a pulse width based on the time for which the SR_DRAIN voltage is greater than VBUS_IN output from the secondary-side of the AC-DC converter;
comparing the volt-sec to a reference voltage (Vref), and when volt-sec is greater than Vref, generating a volt-sec based negative voltage sensed (NSN) detect signal;
determining the pulse width of the integ_resetb signal using a counter and when pulse width exceeds a reference pulse width by greater than a predetermined percentage, generating a counter-expiry signal; and
logically combining the volt-sec based NSN detect signal and the counter-expiry signal to generate a combined NSN detect signal when one or both of the volt-sec based NSN detect signal and the counter-expiry signal are present.