US 12,451,808 B2
Optimizing dead-time between end of on-phase of a high-side switch and beginning of on-phase of a low-side switch in a switching converter
Arnold J D'Souza, Bangalore (IN); and Shyam Somayajula, Bangalore (IN)
Assigned to Shaoxing Yuanfang Semiconductor Co., Ltd., Zhejiang (CN)
Filed by Shaoxing Yuanfang Semiconductor Co., Ltd., Shaoxing (CN)
Filed on May 3, 2023, as Appl. No. 18/311,257.
Claims priority of application No. 202241058857 (IN), filed on Oct. 14, 2022.
Prior Publication US 2024/0128873 A1, Apr. 18, 2024
Int. Cl. H02M 3/158 (2006.01); H02M 1/00 (2007.01)
CPC H02M 3/1584 (2013.01) [H02M 1/0009 (2021.05); H02M 1/0012 (2021.05)] 17 Claims
OG exemplary drawing
 
1. A switching converter comprising:
a high-side switch and a low-side switch coupled in series at a series node, and together operable to generate an output voltage at an output node based on an input voltage received at an input node;
a gate driver block to drive a control terminal of said high-side switch by a high-side drive signal to cause said high-side switch to be ON or OFF, said gate driver block to drive a control terminal of said low-side switch by a low-side drive signal to cause said low-side switch to be ON or OFF;
a first transistor, a second transistor, and a pull-up element,
wherein a series arrangement of said first transistor and said second transistor is coupled between a first terminal of said pull-up element and a first constant reference potential,
wherein a second terminal of said pull-up element is coupled to a second constant reference potential,
wherein a control terminal of said first transistor is coupled to said series node,
wherein a control terminal of said second transistor is coupled to said control terminal of said low-side switch,
wherein a voltage at a junction of said pull-up element and said series arrangement represents a binary-level overlap indicator that indicates whether an ON-duration of said high-side switch overlaps with an ON-duration of said low-side switch.