US 12,451,631 B2
Interconnect substrate including substrates and connector disposed in recess
Atsuto Yoda, Nagano (JP)
Assigned to SHINKO ELECTRIC INDUSTRIES CO., LTD., Nagano (JP)
Filed by SHINKO ELECTRIC INDUSTRIES CO., LTD., Nagano (JP)
Filed on Jan. 27, 2023, as Appl. No. 18/160,365.
Claims priority of application No. 2022-015631 (JP), filed on Feb. 3, 2022.
Prior Publication US 2023/0246362 A1, Aug. 3, 2023
Int. Cl. H01R 12/72 (2011.01); H01R 12/52 (2011.01); H05K 1/14 (2006.01); H05K 3/36 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/16 (2023.01); H01R 12/51 (2011.01); H01R 12/71 (2011.01)
CPC H01R 12/722 (2013.01) [H01R 12/52 (2013.01); H05K 1/14 (2013.01); H05K 1/144 (2013.01); H05K 3/368 (2013.01); H01L 23/3128 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/538 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 25/165 (2013.01); H01R 12/51 (2013.01); H01R 12/523 (2013.01); H01R 12/71 (2013.01); H01R 12/712 (2013.01); H01R 12/714 (2013.01); H01R 12/716 (2013.01); H01R 12/718 (2013.01); H01R 12/728 (2013.01); H05K 1/145 (2013.01); H05K 3/36 (2013.01); H05K 2201/04 (2013.01); H05K 2201/042 (2013.01); H05K 2201/095 (2013.01); H05K 2201/09545 (2013.01); H05K 2201/096 (2013.01); H05K 2201/10227 (2013.01); H05K 2201/10234 (2013.01); H05K 2201/10378 (2013.01); H05K 2201/10734 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An interconnect substrate, comprising:
a first interconnect substrate having a first electrode on a first surface thereof and having a recess formed in an edge thereof in a plan view normal to the first surface;
a second interconnect substrate having a second electrode on a second surface thereof facing toward the first surface;
a connector disposed inside the recess and electrically connected to the first interconnect substrate;
an intermediate substrate disposed between the first interconnect substrate and the second interconnect substrate, the intermediate substrate including an insulating base and a conductive via, the insulating base having a through hole extending from a third surface thereof facing the first surface to a fourth surface thereof facing the second surface, the conductive via being disposed in the through hole;
a first conductive member electrically connecting the first electrode and the conductive via; and
a second conductive member electrically connecting the second electrode and the conductive via,
wherein the insulating base of the intermediate substrate does not overlap the connector in the plan view, and includes a first region and a second region, the first region extending in a predetermined direction in the plan view, the second region located opposite the first region across the recess in the plan view and extending in the predetermined direction in the plan view.