| CPC H01L 25/18 (2013.01) [H01L 23/481 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/09 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H10B 80/00 (2023.02); H01L 2224/05647 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/09519 (2013.01); H01L 2224/29186 (2013.01); H01L 2224/32145 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/05442 (2013.01)] | 19 Claims |
|
1. A semiconductor package, comprising:
a first semiconductor chip comprising:
a first semiconductor substrate comprising:
a first active surface; and
a first inactive surface opposite to the first active surface; and
a plurality of first chip pads disposed on the first active surface;
a second semiconductor chip comprising:
a second semiconductor substrate comprising:
a second active surface; and
a second inactive surface opposite to, the second active surface; and
a plurality of second chip pads disposed on the second active surface, wherein the second semiconductor chip is disposed on the first semiconductor chip with the second active surface of the second semiconductor chip facing the first inactive surface of the first semiconductor chip;
an inter-wiring insulation layer surrounding the plurality of second chip pads;
a bonding insulation material layer interposed between the first semiconductor chip and the second semiconductor chip, the bonding insulation material layer comprising:
a front insulation material portion;
a rear insulation material portion disposed below the front insulation material portion in a vertical direction perpendicular to the first semiconductor substrate and the second semiconductor substrate; and
a bonding insulation material portion disposed such that the front insulation material portion, the bonding insulation material portion, and the rear insulation material portion are stacked along the vertical direction, wherein the bonding insulation material portion includes a material that differs from a material of the front insulation material portion and a material of the rear insulation material portion;
a plurality of bonding pads that electrically connect the first semiconductor chip to the second semiconductor chip, each bonding pad of the plurality of bonding pads comprising:
a pad portion on a respective one of the plurality of second chip pads, wherein the pad portion is surrounded by the inter-wiring insulation layer, the front insulation material portion, and the bonding insulation material portion; and
a through via portion passing through the first semiconductor substrate and having a horizontal width which is less than a horizontal width of the pad portion, wherein at least part of the through via portion is surrounded by the rear insulation material portion.
|