US 12,451,467 B2
Semiconductor device having a redistribution bonding interconnection, a method of manufacturing the semiconductor device, and a chip stack package including the semiconductor device
Si Yun Kim, Icheon-si (KR); Kang Hun Kim, Icheon-si (KR); and Jun Yong Song, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jun. 8, 2022, as Appl. No. 17/835,322.
Claims priority of application No. 10-2022-0008773 (KR), filed on Jan. 20, 2022.
Prior Publication US 2023/0230960 A1, Jul. 20, 2023
Int. Cl. H01L 25/00 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 21/78 (2013.01); H01L 24/05 (2013.01); H01L 24/48 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/48227 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a chip body;
a circuit layer over the chip body;
an upper insulating layer over the circuit layer;
a chip metal layer over the upper insulating layer, the chip metal layer including a pad portion;
a passivation layer over the chip metal layer;
a lower redistribution insulating layer over the passivation layer, the pad portion of the chip metal layer left exposed by the passivation layer and the lower redistribution insulating layer;
a seed layer over the lower redistribution insulating layer;
a redistribution bonding interconnection over the seed layer; and
an upper redistribution insulating layer over the redistribution bonding interconnection,
wherein the redistribution bonding interconnection comprises:
a pad connection portion electrically connected to the pad portion of the chip metal layer;
a horizontal extension portion extending from the pad connection portion to a side surface of the chip body;
a vertical extension portion disposed over the side surface of the chip body, the vertical extension portion extending downward from a side end portion of the horizontal extension portion; and
a bonding portion disposed over the side surface of the chip body,
wherein the bonding portion is positioned at a lower end portion of the vertical extension portion,
wherein end portions of the seed layer and the lower redistribution insulating layer are exposed under the bonding portion of the redistribution bonding interconnection on the side surface of the chip body.