US 12,451,465 B2
Semiconductor device
Yasutaka Shimizu, Tokyo (JP)
Assigned to Mitsubishi Electric Corporation, Tokyo (JP)
Filed by Mitsubishi Electric Corporation, Tokyo (JP)
Filed on Sep. 9, 2022, as Appl. No. 17/930,934.
Claims priority of application No. 2022-070196 (JP), filed on Apr. 21, 2022.
Prior Publication US 2023/0343748 A1, Oct. 26, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/0655 (2013.01) [H01L 23/5386 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/49175 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first circuit pattern having a recessed part in a planar view;
a second circuit pattern positioned in the recessed part;
a plurality of semiconductor chips bonded onto the first circuit pattern; and
wires connecting top electrodes of the plurality of semiconductor chips to the second circuit pattern,
wherein a width of the second circuit pattern increases from upstream to downstream on a current path by which a current is configured to flow through the second circuit pattern,
the first circuit pattern has a step in the planar view on a side of the recessed part, and a width of the recessed part increases in a tiered way to match an increase in the width of the second circuit pattern,
the second circuit pattern includes a first portion, a second portion wider than the first portion, and a third portion wider than the second portion, and
the plurality of semiconductor chips include a first pair of semiconductor chips sandwiching the first portion and having upper electrodes wire-connected to the first portion, a second pair of semiconductor chips sandwiching the second portion and having upper electrodes wire-connected to the second portion, and a third pair of semiconductor chips sandwiching the third portion and having upper electrodes wire-connected to the third portion.