US 12,451,462 B2
Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same
Weihua Cheng, Wuhan (CN); and Jun Liu, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Apr. 17, 2023, as Appl. No. 18/135,453.
Application 18/135,453 is a continuation of application No. 17/499,134, filed on Oct. 12, 2021, granted, now 11,694,993.
Application 17/499,134 is a continuation of application No. 16/669,450, filed on Oct. 30, 2019, granted, now 11,158,604.
Application 16/669,450 is a continuation of application No. PCT/CN2019/105292, filed on Sep. 11, 2019.
Claims priority of application No. PCT/CN2019/082607 (WO), filed on Apr. 15, 2019; application No. PCT/CN2019/085237 (WO), filed on Apr. 30, 2019; and application No. PCT/CN2019/097442 (WO), filed on Jul. 24, 2019.
Prior Publication US 2023/0253364 A1, Aug. 10, 2023
Int. Cl. H10B 10/00 (2023.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 12/00 (2023.01)
CPC H01L 25/0652 (2013.01) [H01L 21/78 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 10/18 (2023.02); H10B 12/50 (2023.02); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device in a multi-chip package (MCP), comprising:
a controller comprising a processor on a substrate and an array of static random-access memory (SRAM) cells on the substrate and outside of the processor;
at least one non-volatile memory die comprising an array of non-volatile memory cells and connected to the controller through wire bonding;
at least one volatile memory die comprising an array of volatile memory cells and connected to the controller through wire bonding; and
at least one control and sensing circuit on the substrate and outside the processor, and configured to control at least one of the array of non-volatile memory cells or the array of volatile memory cells,
wherein the controller is configured to control operations of the at least one non-volatile memory die and the at least one volatile memory die,
wherein the at least one control and sensing circuit comprises a first control and sensing circuit configured to control the array of volatile memory cells, and
wherein the first control and sensing circuit comprises at least one of a row decoder or a column decoder.