US 12,451,453 B2
Semiconductor device, substrate, and method for manufacturing semiconductor device
Keiichi Niwa, Yokkaichi Mie (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Aug. 25, 2022, as Appl. No. 17/895,397.
Claims priority of application No. 2021-192230 (JP), filed on Nov. 26, 2021.
Prior Publication US 2023/0170321 A1, Jun. 1, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 24/14 (2013.01) [H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/14051 (2013.01); H01L 2224/16227 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06575 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01); H01L 2924/3511 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate having a first surface, a second surface opposite to the first surface, a plurality of conductive connections provided on the first surface, and a plurality of columnar electrodes each extending from a corresponding one of the plurality of conductive connections toward the second surface, each of the plurality of columnar electrodes having a tapered shape; and
a semiconductor chip having a third surface facing the first surface and a plurality of connection bumps provided on the third surface, each of the plurality of connection bumps electrically connected to a corresponding one of the plurality of conductive connections, wherein
a first one of the columnar electrodes, located in a first region of a chip region, has a first tapered shape, and a second one of the columnar electrodes, located in a second region of the chip region, has a second tapered shape different from the first tapered shape.