US 12,451,452 B2
Three-dimensional memory and fabrication method thereof
Yuancheng Yang, Wuhan (CN); Wenxi Zhou, Wuhan (CN); Zhiliang Xia, Wuhan (CN); Wei Liu, Wuhan (CN); and Zongliang Huo, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Jul. 27, 2022, as Appl. No. 17/875,016.
Application 17/875,016 is a continuation of application No. PCT/CN2021/115395, filed on Aug. 30, 2021.
Prior Publication US 2023/0068995 A1, Mar. 2, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 24/08 (2013.01) [H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 20 Claims
OG exemplary drawing
 
12. A three-dimensional (3D) memory, comprising:
a memory chip comprising a memory cell array on a common source layer, and a plurality of third contacts penetrating the common source layer and in direct contact with a first pad-out structure on a first side of the common source layer away from the memory cell array;
a first peripheral circuit chip, comprising a first semiconductor layer disposed on the memory chip, and a plurality of first contacts penetrating the first semiconductor layer and in direct contact with a first side of the first semiconductor layer away from the memory cell array, wherein the first peripheral circuit chip is electrically connected with the memory chip through the plurality of first contacts; and
a second peripheral circuit chip, comprising a second semiconductor layer disposed on the first peripheral circuit chip, and a plurality of second contacts penetrating the second semiconductor layer and in direct contact with a first side of the second semiconductor layer away from the memory cell array, wherein the second peripheral circuit chip is electrically connected with the memory chip through the plurality of first and second contacts.