US 12,451,451 B2
Bonded assembly including interconnect-level bonding pads and methods of forming the same
Kensuke Ishikawa, Yokkaichi (JP); Shingo Totani, Yokkaichi (JP); Fumitaka Amano, Yokkaichi (JP); and Rahul Sharangpani, Fremont, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Jun. 30, 2022, as Appl. No. 17/809,991.
Application 17/809,991 is a continuation in part of application No. 17/542,963, filed on Dec. 6, 2021, granted, now 12,347,804.
Application 17/542,963 is a continuation in part of application No. 17/118,036, filed on Dec. 10, 2020, granted, now 11,527,500.
Application 17/118,036 is a continuation in part of application No. 16/825,304, filed on Mar. 20, 2020, granted, now 11,201,139.
Prior Publication US 2022/0336394 A1, Oct. 20, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/08 (2013.01) [H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/03848 (2013.01); H01L 2224/05009 (2013.01); H01L 2224/05011 (2013.01); H01L 2224/05017 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05084 (2013.01); H01L 2224/05087 (2013.01); H01L 2224/05088 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05187 (2013.01); H01L 2224/05541 (2013.01); H01L 2224/05551 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05576 (2013.01); H01L 2224/05578 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05687 (2013.01); H01L 2224/06131 (2013.01); H01L 2224/06163 (2013.01); H01L 2224/06177 (2013.01); H01L 2224/0801 (2013.01); H01L 2224/08055 (2013.01); H01L 2224/08059 (2013.01); H01L 2224/08121 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1438 (2013.01); H01L 2924/37001 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A bonded assembly, comprising:
a first semiconductor die that comprises first semiconductor devices, first interconnect-level dielectric material layers embedding first metal interconnect structures, and first metallic bonding structures embedded within a first bonding-level dielectric layer; and
a second semiconductor die that comprises second semiconductor devices, second interconnect-level dielectric material layers embedding second metal interconnect structures, and second metallic bonding structures embedded within a second bonding-level dielectric layer and bonded to the first metallic bonding structures by metal-to-metal bonding,
wherein one of the first metallic bonding structures comprises:
a pad portion; and
a via portion located between the pad portion and the first semiconductor device, the via portion having second tapered sidewalls.