US 12,451,449 B2
Semiconductor package, and method of manufacturing the same
Wonil Lee, Hwaseong-si (KR); Minki Kim, Suwon-si (KR); Jihoon Kim, Cheonan-si (KR); and Gwangjae Jeon, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 26, 2022, as Appl. No. 17/896,638.
Claims priority of application No. 10-2021-0154537 (KR), filed on Nov. 11, 2021.
Prior Publication US 2023/0141447 A1, May 11, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/05 (2013.01) [H01L 24/03 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 24/94 (2013.01); H01L 24/97 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 24/16 (2013.01); H01L 2224/03616 (2013.01); H01L 2224/05015 (2013.01); H01L 2224/05018 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05187 (2013.01); H01L 2224/05541 (2013.01); H01L 2224/05555 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/05578 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05687 (2013.01); H01L 2224/08121 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/80204 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/95001 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/35121 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a first semiconductor chip comprising a first substrate, a first pad above the first substrate, and a first insulating layer above the first substrate and surrounding the first pad; and
a second semiconductor chip on the first semiconductor chip, the second semiconductor chip comprising a second substrate, a second pad below the second substrate and contacting the first pad, and a second insulating layer below the second substrate, surrounding the second pad, and contacting the first insulating layer,
wherein the first insulating layer comprises a first recess spaced apart from the first pad in a first direction,
wherein the second insulating layer comprises a second recess spaced apart from the second pad in the first direction, the second recess overlapping at least a portion of the first recess in a second direction, perpendicular to the first direction, with an air gap between the first recess and the second recess, and
wherein the semiconductor package further comprises:
a first bonding surface that is defined by the first insulating layer and the second insulating layer contacting each other on one side of the air gap, adjacent to the first pad and the second pad; and
a second bonding surface that is defined by the first insulating layer and the second insulating layer contacting each other on another side of the air gap, that is opposite to the one side.