US 12,451,446 B2
RFLDMOS device and manufacturing method thereof
Han Yu, Shanghai (CN); Jinming Zhang, Shanghai (CN); and Bing Li, Shanghai (CN)
Assigned to SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION, Shanghai (CN)
Filed by Shanghai Huahong Grace Semiconductor Manufacturing Corporation, Shanghai (CN)
Filed on Nov. 9, 2022, as Appl. No. 17/983,788.
Claims priority of application No. 202111520626.1 (CN), filed on Dec. 13, 2021.
Prior Publication US 2023/0187385 A1, Jun. 15, 2023
Int. Cl. H01L 23/60 (2006.01); H01L 23/66 (2006.01); H10D 30/01 (2025.01); H10D 30/65 (2025.01); H01L 23/522 (2006.01); H10D 64/00 (2025.01)
CPC H01L 23/60 (2013.01) [H01L 23/66 (2013.01); H10D 30/0281 (2025.01); H10D 30/65 (2025.01); H01L 23/5225 (2013.01); H01L 2223/6616 (2013.01); H10D 64/112 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A method for manufacturing an RFLDMOS device, comprising the following steps:
step 1: providing a substrate, wherein an epitaxial layer is arranged on the substrate, and a drift region and a body region are arranged in the epitaxial layer; a drain region is arranged in the drift region; a heavily doped region and a source region are arranged in the body region; a polysilicon gate is arranged on the surface of the epitaxial layer; and a metal silicide is arranged on the surface of the polysilicon gate, the source region and the drain region;
step 2: depositing, above the epitaxial layer, a first layer of a dielectric layer and a first layer of a Faraday shielding layer in sequence;
step 3: etching, by utilizing a photolithographic and an etching process, the first layer of a Faraday shielding layer to form a first layer of a Faraday shielding cover;
step 4: depositing a second layer of a dielectric layer, and removing, by utilizing the photolithographic and etching processes, part of the second layer of a dielectric layer covering the first layer of a Faraday shielding cover, so as to expose part of the first layer of a Faraday shielding cover;
step 5: depositing a second layer of a Faraday shielding layer, and forming, by utilizing the photolithographic and etching processes, a second layer of a Faraday shielding cover, wherein the first layer of a Faraday shielding cover and the second layer of a Faraday shielding cover form an interconnection structure;
step 6: depositing a metal front dielectric layer, opening, by photolithography and dry etching, the metal front dielectric layer, and further etching the epitaxial layer to form a deep trench, wherein the bottom of the deep trench is located in the substrate;
step 7: etching a contact hole and depositing a metal to form a sinking channel and the contact hole; and
step 8: forming and etching a first metal layer, and connecting with the contact hole and the sinking channel.